1. Field of the Invention
This invention relates to multiprocessor computer systems having a plurality of processors interconnected through a shared bus, and more particularly, to a message-passing technique which enables the processors to perform asynchronous communication.
2. Description of the Related Art
Tightly coupled multiprocessor systems having a plurality of processor modules interconnected through a shared bus have been proposed and are being used in practice. In such tightly coupled multiprocessor systems, a plurality of processors proceed with their processing by reading from and writing to a shared memory. In order for the system to perform parallel processing, a mechanism for synchronization among processors is indispensable. The synchronization mechanism has a significant effect on the efficiency of the entire system.
A multiprocessor system of a shared memory type, in general, maintains synchronization among the processors by using a shared variable in the shared memory. Since events asynchronously generated cannot be efficiently communicated among the processors without the shared variable, a mechanism for permitting the processors to asynchronously interrupt one another is required.
A multiprocessor workstation proposed by the present inventors et al. ("High-performance Multiprocessor Work Station TOP-1", Shimizu, Ohba, Moriwaki, Nakada and Obara, Symposium of Parallel Processing JSPP '89, pp. 155-162) is equipped with message-passing hardware that permits processors to perform event-driven communications and request interruptions among themselves. This workstation has two kinds of message-passing schemes which differ depending upon whether the message is actually received by a receiving processor or destination processor. The messages from these two schemes are referred to herein as an "Everybody Message" (Message to all destinations) and an "Anybody Message" (Message to a desired destination).
In the "Everybody Message" scheme, message passing is successfully performed if all of the processors designated as destinations are ready for receipt of a message. Each processor in the disclosed system has a reception buffer. If a reception buffer is not vacant even in one of the destination processors such that the message is not received in all of the destination processors, the message passing scheme fails. The failure is detected by the transmitting processor. This method is effective for interruption of all processors and is desirable for coherency control of a TLB (Translation Look-aside Buffer) or the like.
In the "Anybody Message" scheme, message passing is successful if at least one of the destination processors is ready for the reception of a message. Message passing fails only when none of the processors is ready for reception. This method is effective for dispatching a given process to an arbitrary processor.
There are, however, other destination operations that have not been realized by these two kinds of message schemes. Consider, for example, a system in which eight processors send messages to one another. Neither of the above schemes allows one of the processors to send an interrupt to an arbitrary one of the other seven processors (although it has been possible to designate a particular processor as a target). Also, it has not been possible for a processor to send, for instance, a message to four or more of seven processors. It has also been impossible to make, for example, two arbitrary processors stop their current processes and assign to them new processes with hardware alone.
JA PUPA 1-251154 discloses a method for sending a message to processors of a designated class. IBM Technical Disclosure Bulletin, V. 31, No. 6, p 438 discloses a method of sending a message together with the IDs of processors who are to respond to the message.